AT86RF231 datasheet(34/180 Pages) ATMEL

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8111A–AVR–05/08

AT86RF231

pin 8 (/RST). A successful state change can be verified by reading the radio transceiver status

from register 0x01 (TRX_STATUS).

If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF231 is on a state

transition. Do not try to initiate a further state change while the radio transceiver is in

STATE_TRANSITION_IN_PROGRESS.

Pin SLP_TR is a multifunctional pin, refer to Section 6.5 “Sleep/Wake-up and Transmit Signal

(SLP_TR)” on page 27. Dependent on the radio transceiver state, a rising edge of pin SLP_TR

causes the following state transitions:

Pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details

refer to Section 9.6.4 “Master Clock Signal Output (CLKM)” on page 117) and forces the radio

transceiver into TRX_OFF state. However, if the device was in P_ON state it remains in the

P_ON state.

For all states except SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead

to a transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states

(BUSY_*), the command FORCE_TRX_OFF interrupts these active processes, and forces an

immediate transition to TRX_OFF. In contrast a TRX_OFF command is stored until an active

state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is

performed.

For a fast transition from receive or active transmit states to PLL_ON state the command

FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this command does not disable

the PLL and the analog voltage regulator AVREG. It is not available in states SLEEP, P_ON,

RESET, TRX_OFF, and all *_NOCLK states.

The completion of each requested state change shall always be confirmed by reading the regis-

ter bits TRX_STATUS (register 0x01, TRX_STATUS).

7.1.2

Basic Operating Mode Description

7.1.2.1

P_ON - Power-On after V

When the external supply voltage (V

DD) is firstly applied to the AT86RF231, the radio transceiver

goes into the P_ON state performing an on-chip reset. The crystal oscillator is activated and the

default 1 MHz master clock is provided at pin 17 (CLKM) after the crystal oscillator has stabi-

lized. CLKM can be used as a clock source to the microcontroller. The SPI interface and digital

voltage regulator are enabled.

The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal

from the microcontroller at pin 8 (/RST) is not necessary, but recommended for hardware / soft-

ware synchronization reasons.

•TRX_OFF

SLEEP

(level sensitive)

•RX_ON

RX_ON_NOCLK

(level sensitive)

• PLL_ON

BUSY_TX

Whereas the falling edge of pin SLP_TR causes the following state transitions:

• SLEEP

TRX_OFF

(level sensitive)

• RX_ON_NOCLK

RX_ON

(level sensitive)

⇒

AT86RF231 Datasheet(PDF) 34 Page - ATMEL Corporation

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