AT86RF231 datasheet(36/180 Pages) ATMEL

36 / 180 page

8111A–AVR–05/08

AT86RF231

Entering the TRX_OFF state from P_ON, SLEEP, or RESET state is indicated by interrupt

IRQ_4 (AWAKE_END).

7.1.2.4

PLL_ON - PLL State

Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG)

first. After the voltage regulator has been settled, the PLL frequency synthesizer is enabled.

When the PLL has been settled at the receive frequency to a channel defined by register bits

CHANNEL (register 0x08, PHY_CC_CCA), a successful PLL lock is indicated by issuing an

interrupt IRQ_0 (PLL_LOCK).

If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled. If the

PLL has not been settled before the state change nevertheless takes place. Even if the register

bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON, actual frame reception can

only start once the PLL has locked.

The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.

7.1.2.5

RX_ON and BUSY_RX - RX Listen and Receive State

In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled.

The AT86RF231 receive mode is internally separated into RX_ON state and BUSY_RX state.

There is no difference between these states with respect to the analog radio transceiver cir-

cuitry, which are always turned on. In both states the receiver and the PLL frequency

synthesizer are enabled.

During RX_ON state the receiver listens for incoming frames. After detecting a valid synchroni-

zation header (SHR), the AT86RF231 automatically enters the BUSY_RX state. The reception

of a valid PHY header (PHR) generates an IRQ_2 (RX_START) and receives and demodulates

the PSDU data.

During PSDU reception the frame data are stored continuously in the Frame Buffer until the last

byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3

(TRX_END) and the radio transceiver reenters the state RX_ON. At the same time the register

bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see

Section 8.2 “Frame Check Sequence (FCS)” on page 85).

Received frames are passed to the frame filtering unit, refer to Section 7.2.3.5 “Frame Filtering”

on page 61. If the content of the MAC addressing fields (refer to IEEE 802.15.4, Section 7.2.1) of

a frame matches to the expected addresses, which is further dependent on the addressing

mode, an address match interrupt IRQ_5 (AMI) is issued, refer to Section 6.6 “Interrupt Logic” on

page 29. The expected address values are to be stored in registers 0x20 - 0x2B (Short address,

PAN-ID and IEEE address). Frame filtering is available in Basic and Extended Operating Mode,

refer to Section 7.2.3.5 “Frame Filtering” on page 61.

Leaving state RX_ON is only possible by writing a state change command to register bits

TRX_CMD in register 0x02 (TRX_STATE).

7.1.2.6

RX_ON_NOCLK - RX Listen State without CLKM

If the radio transceiver is listening for an incoming frame and the microcontroller is not running

an application, the microcontroller may be powered down to decrease the total system power

consumption. This specific power-down scenario for systems running in clock synchronous

mode (see Section 6. “Microcontroller Interface” on page 16), is supported by the AT86RF231

using the state RX_ON_NOCLK.

AT86RF231 Datasheet(PDF) 36 Page - ATMEL Corporation

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