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LTC2452 Datasheet(PDF) 9 Page - Linear Technology |
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LTC2452 Datasheet(HTML) 9 Page - Linear Technology |
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9 / 20 page ![]() LTC2452 9 2452fb APPLICATIONS INFORMATION Figure 4. Data Output Timing D15 LSB SDO SCK D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D0 D1 2452 F04 t1 t3 tKQ tlSCK thSCK t2 CS MSB During the data output operation the CS input pin must be pulled low (CS = LOW). The data output process starts with the most significant bit of the result being present at the SDO output pin (SDO = D15) once CS goes low. A new data bit appears at the SDO output pin after each falling edge detected at the SCK input pin. The output data can be reliably latched by the user using the rising edge of SCK. Conversion Status Monitor For certain applications, the user may wish to monitor the LTC2452 conversion status. This can be achieved by holding SCK HIGH during the conversion cycle. In this condition, whenever the CS input pin is pulled low (CS = LOW), the SDO output pin will provide an indication of the conversion status. SDO = HIGH is an indication of a conversion cycle in progress while SDO = LOW is an indication of a completed conversion cycle. An example of such a sequence is shown in Figure 5. Conversion status monitoring, while possible, is not re- quired for LTC2452 as its conversion time is fixed and equal at approximately 16.6ms (23ms maximum). Therefore, external timing can be used to determine the completion of a conversion cycle. SERIAL INTERFACE The LTC2452 transmits the conversion result and receives the start of conversion command through a synchronous 3-wire interface. This interface can be used during the CONVERT and SLEEP states to assess the conversion status and during the DATA OUTPUT state to read the conversion result, and to trigger a new conversion. Figure 5. Conversion Status Monitoring Mode SLEEP t1 t2 SDO SCK = HIGH CONVERT 2452 F05 CS |
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