LTC2452

11

2452fb

APPLICATIONS INFORMATION

Serial Clock Idle-Low (CPOL = 0) Examples

In Figure 8, following a conversion cycle the LTC2452

automatically enters the low-power sleep state. The user

determines data availability (and the end of conversion)

based upon external timing. The user then pulls CS low

(CS =

↓) and uses 16 clock cycles to transfer the result.

Following the 16th rising edge of the clock, CS is pulled high

(CS =

↑), which triggers a new conversion.

The timing diagram in Figure 9 is identical to that of Figure 8,

except in this case a new conversion is triggered by SCK.

The 16th SCK falling edge triggers a new conversion cycle

and the CS signal is subsequently pulled high.

Examples of Aborting Cycle using CS

For some applications, the user may wish to abort the I/O

cycle and begin a new conversion. If the LTC2452 is in

the data output state, a CS rising edge clears the remain-

ing data bits from the output registers, aborts the output

cycle and triggers a new conversion. Figure 10 shows

an example of aborting an I/O with idle-high (CPOL = 1)

and Figure 11 shows an example of aborting an I/O with

idle-low (CPOL = 0).

A new conversion cycle can be triggered using the CS

signal without having to generate any serial clock pulses

as shown in Figure 12. If SCK is maintained at a low logic

level, after the end of a conversion cycle, a new conver-

Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion

Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion

SCK

SD0

CONVERT

CONVERT

SLEEP

DATA OUTPUT

2452 F08

CS

SD0

SCK

CONVERT

CONVERT

SLEEP

DATA OUTPUT

2452 F09

CS