LTC2488IDE datasheet(18/28 Pages) LINER

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LTC2488

2488f

APPLICATIONS INFORMATION

required. If the data output sequence is aborted prior to

the 8th falling edge of SCK, the new input data is ignored

and the previously selected input channel remains valid.

If the rising edge of ⎯C⎯S occurs after the 8th falling edge

of SCK, the new input channel is loaded and valid for the

next conversion cycle.

Internal Serial Clock, 3-Wire I/O, Continuous

Conversion.

This timing mode uses a 3-wire interface. The conversion

result is shifted out of the device by an internally generated

serial clock (SCK) signal (see Figure 9). In this case, ⎯C⎯S is

permanently tied to ground, simplifying the user interface

or transmission over an isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 4ms after VCC exceeds 2V. An internal weak

pull-up is active during the POR cycle; therefore, the internal

serial clock timing mode is automatically selected if SCK

is ﬂoating or driven HIGH.

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (⎯E⎯O⎯C = 1). Once the conversion is

complete, SCK and SDO go LOW (⎯E⎯O⎯C = 0) indicating

the conversion has ﬁnished and the device has entered

the sleep state. The device remains in the sleep state a

minimum amount of time (1/2 the internal SCK period)

then immediately begins outputting and inputting data.

The input data is shifted through the SDI pin on the ris-

ing edge of SCK (including the ﬁrst rising edge) and the

output data is shifted out the SDO pin on the falling edge

of SCK. The data input/output cycle is concluded and a

new conversion automatically begins after the 24th rising

edge of SCK. During the next conversion, SCK and SDO

remain HIGH until the conversion is complete.

The Use of a 10k Pull-Up on SCK for Internal SCK

Selection

If ⎯C⎯S is pulled HIGH while the converter is driving SCK

LOW, the internal pull-up is not available to restore SCK

to a logic HIGH state if SCK is ﬂoating. This will cause the

device to exit the internal SCK mode on the next falling

edge of ⎯C⎯S. This can be avoided by adding an external 10k

pull-up resistor to the SCK pin.

Figure 7. Internal Serial Clock, Single Cycle Operation

VCC

SCK

SDI

GND

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUTS

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

LTC2488

4-WIRE

SPI INTERFACE

OPTIONAL

10k

VCC

REF+

REF–

CH0

CH1

CH2

CH3

COM

2.7V TO 5.5V

0.1

µF

SDO

Hi-Z

2488 F07

SCK

(INTERNAL)

SDI

SDO

CONVERSION

SLEEP

DATA INPUT/OUTPUT

CONVERSION

EOC

SGL

ODD

DON'T CARE

MSB

SIG

“0”

<tEOCTEST

LSB

BIT 23

BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

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