LTC2488IDE datasheet(5/28 Pages) LINER

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LTC2488

2488f

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fEOSC

External Oscillator Frequency Range

(Note 16)

●

4000

kHz

tHEO

External Oscillator High Period

●

0.125

100

µs

tLEO

External Oscillator Low Period

●

0.125

100

µs

tCONV

Conversion Time

Simultaneous 50Hz/60Hz

External Oscillator

●

144.1

146.9

41036/fEOSC (in kHz)

149.9

fISCK

Internal SCK Frequency

Internal Oscillator (Notes 10, 17)

External Oscillator (Notes 10, 11, 15)

38.4

fEOSC/8

kHz

DISCK

Internal SCK Duty Cycle

(Notes 10, 17)

●

fESCK

External SCK Frequency Range

(Notes 10, 11, 15)

●

4000

kHz

tLESCK

External SCK Low Period

(Notes 10, 11, 15)

●

125

tHESCK

External SCK High Period

(Notes 10, 11, 15)

●

125

tDOUT_ISCK

Internal SCK 24-Bit Data Output Time

Internal Oscillator (Notes 10, 17)

External Oscillator (Notes 10, 11, 15)

●

0.61

0.625

192/fEOSC (in kHz)

0.64

tDOUT_ESCK

External SCK 24-Bit Data Output Time

24/fESCK (in kHz)

⎯C⎯S↓ to SDO Low

●

200

⎯C⎯S↑ to SDO High Z

●

200

⎯C⎯S↓ to SCK↓

Internal SCK Mode

●

200

⎯C⎯S↓ to SCK↑

External SCK Mode

●

tKQMAX

SCK↓ to SDO Valid

●

200

tKQMIN

SDO Hold After SCK↓

(Note 5)

●

SCK Set-Up Before ⎯C⎯S↓

●

SDI Setup Before SCK↑

(Note 5)

●

100

SDI Hold After SCK↑

(Note 5)

●

100

DIGITAL INPUTS AND DIGITAL OUTPUTS The ● denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: Unless otherwise speciﬁed:

VCC = 2.7V to 5.5V

VREFCM = VREF/2, FS = 0.5VREF

VIN = IN

+ – IN–, VIN(CM) = (IN+ – IN–)/2,

where IN+ and IN– are the selected input channels.

Note 4: Use internal conversion clock or external conversion clock source

with fEOSC = 307.2kHz unless other wise speciﬁed.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: fEOSC = 256kHz ±2% (external oscillator).

Note 8: fEOSC = 307.2kHz ±2% (external oscillator).

Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz

±2% (external oscillator).

Note 10: The SCK can be conﬁgured in external SCK mode or internal SCK

mode. In external SCK mode, the SCK pin is used as a digital input and the

driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a

digital output and the output clock signal during the data output is fISCK.

Note 11: The external oscillator is connected to the FO pin. The external

oscillator frequency, fEOSC, is expressed in kHz.

Note 12: The converter uses its internal oscillator.

Note 13: The output noise includes the contribution of the internal

calibration operations. VREF ≤ VCC.

Note 14: Guaranteed by design and test correlation.

Note 15: The converter is in external SCK mode of operation such that the

SCK pin is used as a digital input. The frequency of the clock signal driving

SCK during the data output is fESCK and is expressed in Hz.

Note 16: Refer to Applications Information section for performance vs

data rate graphs.

Note 17: The converter in internal SCK mode of operation such that the

SCK pin is used as a digital output.

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