LTC2488IDE datasheet(20/28 Pages) LINER

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LTC2488

2488f

APPLICATIONS INFORMATION

Whenever SCK is LOW, the LTC2488’s internal pull-up at

SCK is disabled. Normally, SCK is not externally driven if

the device is operating in the internal SCK timing mode.

However, certain applications may require an external

driver on SCK. If the driver goes Hi-Z after outputting a

LOW signal, the internal pull-up is disabled. An external

10k pull-up resistor prevents the device from exiting the

internal SCK mode under this condition.

A similar situation may occur during the sleep state when

⎯C⎯S is pulsed HIGH-LOW-HIGH in order to test the conver-

sion status. If the device is in the sleep state (⎯E⎯O⎯C = 0),

SCK will go LOW. If ⎯C⎯S goes HIGH before the time tEOCtest,

the internal pull-up is activated. If SCK is heavily loaded,

the internal pull-up may not restore SCK to a HIGH state

before the next falling edge of ⎯C⎯S. The external 10k pull-up

resistor prevents the device from exiting the internal SCK

mode under this condition.

PRESERVING THE CONVERTER ACCURACY

The LTC2488 is designed to reduce as much as possible

sensitivity to device decoupling, PCB layout, anti-aliasing

circuits, line frequency perturbations, and temperature

sensitivity. In order to achieve maximum performance a

few simple precautions should be observed.

Digital Signal Levels

The LTC2488’s digital interface is easy to use. Its digital

inputs SDI, FO, ⎯C⎯S, and SCK (in external serial clock mode)

accept standard CMOS logic levels. Internal hysteresis

circuits can tolerate edge transition times as slow as

100µs.

The digital input signal range is 0.5V to VCC – 0.5V. During

transitions, the CMOS input circuits draw dynamic cur-

rent. For optimal performance, application of signals to

the serial data interface should be reserved for the sleep

and data output periods.

During the conversion period, overshoot and undershoot

of fast digital signals applied to both the serial digital in-

terface and the external oscillator pin (FO) may degrade

the converter performance. Undershoot and overshoot

occur due to impedance mismatch of the circuit board

trace at the converter pin when the transition time of an

external control signal is less than twice the propagation

delay from the driver to the input pin. For reference, on a

regular FR-4 board, the propagation delay is approximately

183ps/inch. In order to prevent overshoot, a driver with

a 1ns transition time must be connected to the converter

through a trace shorter than 2.5 inches. This becomes

difﬁcult when shared control lines are used and multiple

reﬂections occur.

Parallel termination near the input pin of the LTC2488 will

eliminate this problem, but will increase the driver power

dissipation. A series resistor from 27Ω to 54Ω (depend-

ing on the trace impedance and connection) placed near

the driver will also eliminate over/under shoot without

additional driver power dissipation.

For many applications, the serial interface pins (SCK, SDI,

⎯C⎯S, FO) remain static during the conversion cycle and

no degradation occurs. On the other hand, if an external

oscillator is used (FO driven externally) it is active during

the conversion cycle. Moreover, the digital ﬁlter rejection

is minimal at the clock rate applied to FO. Care must be

taken to ensure external inputs and reference lines do not

cross this signal or run near it. These issues are avoided

when using the internal oscillator.

Driving the Input and Reference

The input and reference pins of the LTC2488 are connected

directly to a switched capacitor network. Depending on

the relationship between the differential input voltage and

the differential reference voltage, these capacitors are

switched between these four pins. Each time a capacitor

is switched between two of these pins, a small amount

of charge is transferred. A simpliﬁed equivalent circuit is

shown in Figure 10.

When using the LTC2488’s internal oscillator, the input

capacitor array is switched at 123kHz. The effect of the

charge transfer depends on the circuitry driving the in-

put/reference pins. If the total external RC time constant

is less than 580ns the errors introduced by the sampling

process are negligible since complete settling occurs.

Typically, the reference inputs are driven from a low imped-

ance source. In this case, complete settling occurs even

with large external bypass capacitors. The inputs (CH0 to

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