LTC2488IDE datasheet(22/28 Pages) LINER

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LTC2488

2488f

APPLICATIONS INFORMATION

IN– are matched. Mismatches in source impedance lead

to a ﬁxed offset error but do not effect the linearity or full

scale reading. A 1% mismatch in a 1k source resistance

leads to a 74µV shift in offset voltage.

In applications where the common mode input voltage

varies as a function of the input signal level (single ended

type sensors), the common mode input current varies

proportionally with input voltage. For the case of balanced

input impedances, the common mode input current effects

are rejected by the large CMRR of the LTC2488, leading

to little degradation in accuracy. Mismatches in source

impedances lead to gain errors proportional to the dif-

ference between the common mode input and common

mode reference. 1% mismatches in 1k source resistances

lead to gain errors on the order of 15ppm. Based on the

stability of the internal sampling capacitors and the ac-

curacy of the internal oscillator, a one-time calibration will

remove this error.

In addition to the input sampling current, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA Max), results

in a small offset shift. A 1k source resistance will create a

1µV typical and a 10µV maximum offset voltage.

Reference Current

Similar to the analog inputs, the LTC2488 samples the

differential reference pins (REF+ and REF–) transferring

small amounts of charge to and from these pins, thus

producing a dynamic reference current. If incomplete set-

tling occurs (as a function the reference source resistance

and reference bypass capacitance) linearity and gain errors

are introduced.

For relatively small values of external reference capacitance

(CREF < 1nF), the voltage on the sampling capacitor settles

for reference impedances of many kΩ (if CREF = 100pF up

to 10kΩ will not degrade the performance) (see Figures

11 and 12).

In cases where large bypass capacitors are required on

the reference inputs (CREF > 0.01µF) full-scale and linear-

ity errors are proportional to the value of the reference

resistance. Every ohm of reference resistance produces

a full-scale error of approximately 0.5ppm (while operat-

ing with the internal oscillator) (see Figures 13 and 14). If

the input common mode voltage is equal to the reference

common mode voltage, a linearity error of approximately

0.67ppm per 100Ω of reference resistance results (see

Figure 15). In applications where the input and reference

common mode voltages are different, the errors increase.

A 1V difference in between common mode input and

common mode reference results in a 6.7ppm INL error

for every 100Ω of reference resistance.

In addition to the reference sampling charge, the reference

ESD protection diodes have a temperature dependent leak-

age current. This leakage current, nominally 1nA (±10nA

max) results in a small gain error. A 100Ω reference

resistance will create a 0.5µV full scale error.

Figure 11. +FS Error vs RSOURCE at VREF (Small CREF)

Figure 12. –FS Error vs RSOURCE at VREF (Small CREF)

RSOURCE (Ω)

10k

2488 F11

–10

100

100k

VCC = 5V

VREF = 5V

VIN

+ = 3.75V

VIN

– = 1.25V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

RSOURCE (Ω)

–30

–10

10k

2488 F12

–50

–70

–40

–20

–60

–80

–90

100

100k

VCC = 5V

VREF = 5V

VIN

+ = 1.25V

VIN

– = 3.75V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

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