TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

internal timing

The SR and SV signals are required to operate the CDS as previously explained. The user needs to synchronize

the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external circuitry by

the ADCCLK signal that is also used internally to control both ADC and PGA operations. It is required that the

positive half cycle of the ADCCLK signal always falls in between two adjacent SV pulses as shown in Figure 2.

The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal performance.

The TLV987 has direct access to the CDS and PGA internal clocks through the TPP pin and the TPM pin, which

may be used to assist timing alignment. See

test register description paragraph for details.

The CLAMP signal is used to activate the input clamping, and the OBCLP signal is used to activate auto optical

black and offset correction.

input blanking function

During some periods of operation, large input transients may occur at the TLV987 input, which can saturate the

input circuits and cause long recovery time. To prevent circuit saturation under such a situation, the TLV987

includes an input blanking function that blocks the input signals by disabling CDS operation whenever the BLKG

input is pulled low.

3-wire serial interface

A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers of

the TLV987. The serial clock SCLK can be run at a maximum speed of 40 MHz. The serial data SDIN is 16 bits

long. After two leading null bits, there are four address bits for which internal register is to be updated, the

following ten bits are the data to be written to the register. To enable the serial port, the CS pin must be held

low. The data transfer is initiated by the incoming SCLK after CS falls.

device reset

When the reset pin (pin 29) is pulled low, all internal registers are set to their default values. The device also

resets itself when it is first powered on. In addition, the TLV987 has a software-reset function that resets the

device when writing a control bit to the control register.

See

test register description paragraph for the register default values.

voltage references

An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate

the ADC Ref– voltage of 1 V and Ref+ voltage of 2 V. All internally-generated voltages are fixed values and

cannot be adjusted.

power-down mode (standby)

The TLV987 implements both hardware and software power-down modes. Pulling the STBY pin (pin 30) low

puts the device in the low-power stand-by mode. Total supply current drops to about 0.6 mA. Setting a

power-down control bit in the control register can also activate the power-down mode. The user can still program

all internal registers during the power-down mode.