TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

18

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

First Line

CCD

1

CCD

2

CCD

3

CCD

4

CCD

1

CCD

2

CCD

3

CCD

4

2∧N+1 PIXELS

During this interval an offset of 255 LSB is

intentionally added to the PGA output (see Note)

ADC OUT

for black pixels

OBLC (internal)

OBPC (internal)

ADD255 (internal)

ADCCLK

OBCLP

CDS OUT (internal)

CCD output

SV

SR

PGA samples

”CCD1”

Initiates internal counters, etc.

ADC

1

ADC

2

ADC

3

ADC

4

Second Line

2∧N+1 PIXELS

DACs are updated

3 half cycles

allow settling

Latency = 4.5 Cycles

Figure 6. Optical Black and Offset Correction Timing

To avoid the ADC being clipped on differential negative input signals, an internal offset that is equal to 255 ADC

LSBs is intentionally added to the PGA output signal. This offset is only added during the optical black pixel

internal latency adjustment.