TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

15

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

power supply

requiring different supply voltages.

grounding and decoupling

General practices should apply to the PCB design to limit high frequency transients and noise that are fed back

into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.

In the case of power supply decoupling, 0.1-

µF ceramic chip capacitors are adequate to keep the impedance

low over a wide frequency range. Recommended external decoupling for the three voltage reference pins is

shown in Figure 3. Since their effectiveness depends largely on the proximity to the individual supply pin, all

decoupling capacitors should be placed as close to the supply pins as possible.

To reduce high frequency and noise coupling, it is highly recommended that the digital ground and analog

ground be shorted immediately outside the package. This can be accomplished by running a low impedance

line between the DGND and AGND pins, under the package.

automatic optical black and offset correction

In the TLV987, the optical black and system channel offset corrections are performed by an auto digital feedback

loop. Two DACs are used to compensate for both channel offset and the optical black offset. A coarse correction

DAC (CDAC) is located before the PGA gain stage and a fine correction DAC (FDAC) is located after the gain

stage. The digital calibration system is capable of correcting the optical black and channel offset down to one

ADC LSB accuracy.

The TLV987 automatically starts auto-calibration whenever the OBCLP input is pulled low. The OBCLP pulse

should be wide enough to cover one positive half cycle of the ADCCLK as shown in Figure 1.

For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the

ADC. A digital circuit averages the data during the optical black pixels. The final averaged result is compared

digitally with the desired output code stored in the Vb register (default is 40h), then control logic adjusts the

FDAC to make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (

±255 ADC LSBs),

the error is corrected by both the CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB

depending on whether the offset is negative or positive, until the output is within the range of the FDAC. The

remaining residue is corrected by the FDAC.

The relationship among the FDAC, CDAC, and ADC in terms of the number of ADC LSBs is as follows:

1 FDAC LSB = 1 ADC LSB,

1 CDAC LSB = 0.5 x PGA linear gain

× 1 ADC LSB.

For example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 1 ADC LSB.

After auto-calibration is complete, the ADC digital output during CCD signal interval can be expressed by the

following equation:

ADC output [D9–D0] = CCD_input

× PGA gain + Vb,

Where, Vb is the desired black level selected by the user. The total offset including optical black offset is

calibrated to be equal to the Vb by adjusting the offset correction DAC during auto-calibration.