TMS320P15 datasheet(73/146 Pages) TI

73 / 146 page

RL = 825Ω,

CL = 100 pF,

(see Figure 2)

RL = 825Ω,

CL = 100 pF,

(see Figure 2)

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C – JANUARY 1987 – REVISED JULY 1991

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77001

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

td1

Delay time CLKOUT

↓ to address bus valid

10†

td2

Delay time CLKOUT

↓ to MEN↓

1/4 tc(C)–5† 1/4 tc(C)+25

td3

Delay time CLKOUT

↓ to MEN↑

–10†

td4

Delay time CLKOUT

↓ to DEN↓

1/4 tc(C)–5† 1/4 tc(C)+25

td5

Delay time CLKOUT

↓ to DEN↑

–10†

td6

Delay time CLKOUT

↓ to WE↓

1/2 tc(C)–5† 1/2 tc(C)+25

td7

Delay time CLKOUT

↓ to WE↑

–10†

td8

Delay time CLKOUT

↓ to data bus OUT valid

1/4 tc(C)+75

td9

Time after CLKOUT

↓ that data bus starts to be driven

1/4 tc(C)–5†

td10

Time after CLKOUT

↓ that data bus stops being driven

1/4 tc(C)+60

Data bus OUT valid after CLKOUT

↓

1/4 tc(C)–10

th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 14)

0†

tsu(A-MD)

Address bus setup time to DEN

↓

– 4†

† Values derived from characterization data and not tested.

NOTE 14: Address bus will be valid upon WE

↑, MEN↑, or DEN↑.

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tsu(D)

Setup time data bus valid prior to CLKOUT

↓

th(D)

Hold time, data bus held valid after CLKOUT

↓ (see Note 9)

NOTE 9:

Data may be removed from the data bus upon MEN

↑ or DEN↑ preceding CLKOUT↓.

TMS320P15 Datasheet(PDF) 73 Page - Texas Instruments

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