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TMS320P15 Datasheet(PDF) 32 Page - Texas Instruments

Part # TMS320P15
Description  DIGITAL SIGNAL PROCESSORS
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320P15 Datasheet(HTML) 32 Page - Texas Instruments

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TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C – JANUARY 1987 – REVISED JULY 1991
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77001
32
functional block diagram
WE
REN
RS
IOP0-IOP15
RXD
TXD
CAP0,1
CMP4, 5 /
CAP2, 3
CMP0-CMP3
IOP
9
9
Serial
Port
Timer
Serial
Port
Controller
CAP
Detect
(4)
4
16
4
× 16
FIFO
Stack
(4)
16
6
16
16
ACT
(6)
CMPR
(6)
32
WDT
D15-D0
TCLK1.2
16
Watchdog Timer
12
12
32
16
16
16
32
Shifter (0,1,4)
32
ACC (32)
32
Data
(256 Words)
Address
Data
32
32
16
P(32)
T(16)
Multiplier
Shifter
(0–16)
16
8
DP
7
8
8
AR1 (16)
AR0 (16)
ARP
16
16
16
16
16
A0-A11
PA0-PA2
16
Instruction
Program
ROM/EPROM
(4K Words)
3
Stack
4
× 12
12
12
PC (12)
12
12 LSB
16
CLKOUT
CLKIN
Program Bus
Timers
1.2
MUX
MUX
MUX
ALU (32)
Legend:
DP = Data Page Pointer
ACC = Accumulator
IOP = Input/Output Port
ACT = Action Register
(Bit Selectable)
ALU = Arithmetic Logic Unit
PC = Program Counter
ARP = Auxiliary Register Point
P = P Register
AR0 = Auxiliary Register 0
RBR = Receive Buffer Register
AR1 = Auxiliary Register 1
RSR = Receive Shift Register
BSR = Bank Select Register
T = T Register
CAP = Capture
TBR = Transmit Buffer Register
CMPR = Compare Register
TSR = Transmit Shift Register
1
TBR
RBR
TSR
RSR
16
16
Data Bus
16
BSR
16
Interrupt
Controller
NMI/
MC/MP
INT
Data Bus
16
architecture
The
′C1x family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture,
program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution.
The
′C1x family’s modification of a Harvard architecture allows transfers between program and data spaces,
thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory
to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate
instructions and subroutines based on computed values.
32-bit ALU/accumulator
The
′C14/E14/P14 devices contain a 32-bit ALU and accumulator for support of double-precision,
twos-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken
from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the
ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed controller.



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