TERMINAL INFORMATION

TPS51113DRC

TPS51163DRC

1

4

3

2

5

10

7

8

9

6

BOOT

LDRV_OC

HDRV

SW

GND

PGOOD

COMP_EN

FB

VOS

VDD

TPS51113, TPS51163

TERMINAL FUNCTIONS

TERMINAL

PIN

NAME

NO.

I/O

DESCRIPTION

Gate drive voltage for the high-side N-channel MOSFET. Typically, a 100 nF capacitor must be connected between this pin

BOOT

1

I

and SW. Also, a diode from VDD to BOOT should be externally provided.

Output of the error amplifier and the shutdown pin. Pulling the voltage on this pin lower than 800 mV shuts the controller

COMP_EN

7

I/O

down.

Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage of

FB

8

I

800 mV.

GND

5

–

Common reference for the device.

HDRV

3

O

Gate drive output for the high-side N-channel MOSFET.

Gate drive output for the low-side or rectifier MOSFET. The set point is read during start up calibration with the 10

µA

LDRV_OC

4

O

current source present.

PGOOD

10

O

Open drain power good output. An external pull-up resistor is required.

SW

2

O

Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-side FET driver.

VDD

6

I

Power input to the controller, 4.5 V to 13.2 V.

Input to set undervoltage and overvoltage protections. Undervoltage protection occurs when VOS voltage is lower than 600

mV. The controller shuts down with both MOSFETs latched off. Overvoltage protection occurs when VOS voltage is higher

VOS

9

I

than 1V, the upper MOSFET is turned off and the lower MOSFET is forced on until VOS voltage reaches 400 mV. Then the

lower MOSFET is also turned off. After the undervoltage or overvoltage events, normal operation can be restored only by

cycling the VDD voltage.

SON PACKAGE

(TOP VIEW)

6

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