Layout Considerations

TPS51113 Design Example

TPS51113, TPS51163

For the grounding and circuit layout, certain points need to be considered.

• It is important that the signal ground and power ground properly use separate copper planes to prevent the

noise of power ground from influencing the signal ground. The impedance of each ground is minimized by

using its copper plane. Sensitive nodes, such as the FB resistor divider and VOS resistor divider, should be

connected to the signal ground plane, which is also connected with the GND pin of the device. The high

power noisy circuits, such as synchronous rectifier, MOSFET driver decoupling capacitors, the input

capacitors and the output capacitors should be connected to the power ground plane. Finally, the two

separate ground planes should be strongly connected together near the device by using a single path/trace.

• A minimum of 0.1-µF ceramic capacitor must be placed as close to VDD pin and GND pin as possible with a

trace at least 20 mils wide, from the bypass capacitor to the GND. Usually a capacitance value of 1

µF is

recommended for the bypass capacitor.

• The PowerPAD should be electrically connected to GND.

• A parallel pair of trace (with at least 15 mils wide) connects the regulated voltage back to the chip. The trace

should be away from the switching components. The bias resistor of the resistor divider should be connected

to the FB pin and GND pin as close as possible.

• The component placement of the power stage should ensure minimized loop areas to suppress the radiated

emissions. The input current loop is consisted of the input capacitors, the main switching MOSFET, the

inductor, the output capacitors and the ground path back to the input capacitors. The SR MOSFET, the

inductor, the output capacitors and the ground path back to the source of the SR MOSFET consists of the

output current loop. The connection/trace should be as short as possible to reduce the parasitic inductance.

• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. A trace of 25 mils or wider is recommended.

• Connect the overcurrent setting resistor from LDRV_OC to GND close to the device.

The following example illustrates the design process and component selection for a single output synchronous

buck converter using the TPS51113. The schematic of a design example is shown in Figure 9. The specification

of the converter is listed in Table 1.

Table 1. Specification of the Single Output Synchronous Buck Converter

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Input voltage

10.8

12

13.2

V

Output voltage

1.6

V

Output ripple

V

Output current

10

V

Switching frequency

300

kHz

16

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