LT3582 datasheet(12/28 Pages) LINER

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LT3582/LT3582-5/LT3582-12

3582512f

CMDR register. All data written to register addresses 0-2

is stored in REGO-REG2. Regardless of the RSEL bits, OTP

bytes cannot be written directly. See the OTP Program-

ming section for more information.

Data Transfer Protocol

The LT3582 series supports 8-bit data transfers in the

transaction formats shown in Figures 2 and 3 below.

Multiple data bytes can only be transferred by issuing

multiple transactions.

Figure 2 shows the required format for writing a byte of

data to the LT3582 series. Again, the chip address depends

on the CA pin logic state.

SCHIP ADDR

AREG ADDR

DATA

0110 001 OR

1000 101

00000b2:b0

b7:b0

FROM MASTER TO SLAVE

A: ACKNOWLEDGE (LOW)

FROM SLAVE TO MASTER

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

Figure 2: I2C Byte Write Transaction

A byte of data is read from the LT3582 series using the

format shown in Figure 3. This transaction requires four

I2C bytes to read one byte of chip data and must be

repeated for each subsequent byte of data that is read.

SCHIP ADDR

AREG ADDR

0110 001 OR

1000 101

00000b2:b0

Figure 3: I2C Byte Read Transaction

LT3582 Chip Conﬁguration

Settings such as output voltages and sequencing are

digitally programmable. The chip uses settings from either

the REG or OTP bytes, depending on the states of the cor-

responding RSEL bits (0 for OTP and 1 for REG).

During shutdown the RSEL bits are reset low. As a result,

the initial conﬁguration comes from the OTP data bytes.

After power-up, the conﬁguration can be changed by writ-

ing new settings to the appropriate REG data byte(s) then

setting the corresponding RSEL bit(s).

Finally, data in the REG bytes can be permanently pro-

grammed to OTP by applying voltage to the VPP pin and

setting the WOTP bit in the Command Register. See the

OTP Programming section for more information.

LT3582-5/LT3582-12 Chip Conﬁguration

The LT3582-5/LT3582-12 are shipped from the factory

with the OTP memory pre-programmed and LOCKed which

prohibits subsequent changes to the conﬁguration. The

conﬁguration can still be read through the I2C bus and

the RST & SWOFF bits of the CMDR register (described

later) are functional. The following sections describe the

various conﬁgurable features of the LT3582. The LT3582-5

and LT3582-12 are pre-conﬁgured as follows: VP and VN

are programmed for ±5V or ±12V respectively, LOCK = 1,

IRMP = 00, PDDIS = 1, PUSEQ = 11 and VPLUS may be 1

or 0. Since LOCK = 1, subsequent conﬁguration changes

are prohibited. See Conﬁguration Lockout (LOCK Bit) for

more information.

Registers and OTP

The registers and OTP bytes for the LT3582 series are

organized as shown in Table 1. The CMDR is reset to 00h

upon power up, during shutdown and during under-volt-

age and thermal lockouts.

REG0-REG2 are never reset

and must always be loaded with valid data before use.

The LT3582’s OTP memory is shipped with all 0’s, and

as a result, the PUSEQ bits are conﬁgured to disable the

outputs. The PUSEQ bits must be reconﬁgured to enable

the outputs.

APPLICATIONS INFORMATION

SCHIP ADDR

DATA

0110 001 OR

1000 101

b7:b0

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