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LT3582/LT3582-5/LT3582-12

3582512f

under control of its respective RAMP pin (see Figure 8

below). The power-up sequencing concludes when both

outputs have reached regulation.

Evaluating PUSEQ Settings (LT3582 Only): After SHDN

rises, the LT3582 uses the PUSEQ conﬁguration found

in OTP. The effects of differing PUSEQ settings can be

observed without writing to OTP by taking the following

actions:

1. Write the SWOFF bit high, stopping both converters

and discharging the RAMP pins.

2. Write the desired settings to the PUSEQ bits in

REG2.

3. Set the RSEL2 bit high which selects the REG2

conﬁguration settings.

4. Write SWOFF low which restarts both converters.

This will initiate the desired power-up sequence that can

be observed with an oscilloscope.

Power-Down Discharge (PDDIS bit)

The PDDIS bit is used to enable power down discharge.

This bit is pre-conﬁgured to a “1” for the LT3582-5 and

LT3582-12, thus enabling power-down discharge.Setting

APPLICATIONS INFORMATION

PDDIS = 0 disables the power-down discharge causing

the chip to shut down immediately after SHDN falls. The

PDDIS bit must only be set in conjunction with PUSEQ being

set to 11. Driving SHDN low, with power-down discharge

enabled (PDDIS = 1) causes the chip to power-down after

ﬁrst discharging the output voltages. Speciﬁcally, driving

SHDN low causes the following sequence of events to

happen:

1. Both converters are turned off.

2. Discharge currents are enabled to discharge the

output capacitors

• See Electrical Charateristics for IVOUTP-PDS and

ICAPP-PDS which help discharge VOUTP and CAPP

• See Electrical Charateristics for IVOUTN-PDS which

helps discharge VOUTN

3. The chip waits until the output voltages have

discharged to within ~0.5V to ~1.5V of ground.

4. Discharge currents are disabled and the LT3582

powers down.

Figure 8: Power-up Sequencing (PUSEQ=10)

3582512 F08

VVOUTP

5V/DIV

VVOUTN

5V/DIV

VRAMPP

0.5V/DIV

VRAMPN

0.5V/DIV

5ms/DIV

RAMPN

RAMPP

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