MAX9526 datasheet(9/38 Pages) MAXIM

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Low-Power, High-Performance

NTSC/PAL Video Decoder

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Pin Description

QSOP

TQFN-EP

NAME

FUNCTION

130

VIN1

Single-Ended Composite Video Input 1. AC-couple the input video signal with a 0.1µF

capacitor.

231

VREF

Video Reference Bypass. Bypass VREF to AGND with a 0.1µF capacitor as close as

possible to the device.

332

VIN2

Single-Ended Composite Video Input 2. AC-couple the input video signal with a 0.1µF

capacitor.

AGND

Analog Ground

AVDD

Analog Power-Supply Input. Connect to a +1.8V supply. Bypass AVDD to AGND with a

0.1µF capacitor.

XTAL2

External Crystal. Connect XTAL2 to one terminal of the crystal oscillator. Ground XTAL2

when applying an external clock to XTAL/OSC.

XTAL/OSC

External Crystal/Oscillator. Connect XTAL/OSC to one terminal of a crystal or an

external clock source. Connect XTAL2 to the other terminal of the crystal oscillator.

I.C.

Internal connection. Connect to DGND.

DEVADR

I2C Device Address Select Input. Connect to DVDD, DGND, or SDA to select 1 of 3

available I2C slave addresses (see Table 5).

10, 22

7, 21

DVDD

Digital Power-Supply Input. Connect to a +1.8V supply. Bypass DVDD to DGND with a

0.1µF capacitor in parallel with a 10µF capacitor.

11, 23

8, 22

DGND

Digital Ground. Connect both DGND terminals together.

SDA

I2C-Compatible Serial-Data Input/Output. Connect a 10k

Ω pullup resistor from SDA to

DVDDIO for full output swing.

SCL

2C-Compatible Serial-Clock Input. Connect a 10k

Ω pullup resistor from SCL to

DVDDIO for full output swing.

IRQ

Hardware Interrupt Open-Drain Output. If not masked,

IRQ is pulled low when the bits

in the status register change state. Repeated faults have no effect on

IRQ until IRQ is

cleared by reading the corresponding status register. Connect a 10k

Ω pullup resistor

from

IRQ to DVDDIO for full output swing.

15–20, 25–28

13–16, 18,

19, 24, 26,

27, 28

D0–D9

Digital Video Outputs Bit 0–Bit 9, 10-Bit Component Digital Video Outputs. The output

format is 10-bit ITU-R BT.656, 4:2:2 with embedded sync. D1 and D0 can be

configured as horizontal and vertical sync outputs using the Clock and Output register

0x0D. D0 is LSB.

LLC

Line-Locked 27MHz Clock Output. With line-locked mode, the LLC clock varies in

response to horizontal line rate of the incoming video. In async mode, the LLC clock is

synchronous to the crystal (see Table 1).

DVDDIO

Digital I/O Power-Supply Input. Accepts a +1.7V to +3.45V voltage input. Bypass to

DGND with a 0.1µF capacitor.

—

9, 17, 25, 29

N.C.

No Connection. Not internally connected.

—

Exposed Pad. EP is internally connected to GND. Connect EP to GND.

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