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MAX9526 Datasheet(PDF) 29 Page - Maxim Integrated Products |
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MAX9526 Datasheet(HTML) 29 Page - Maxim Integrated Products |
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29 / 38 page ![]() Low-Power, High-Performance NTSC/PAL Video Decoder ______________________________________________________________________________________ 29 ADC-Only Mode (RAWADC) 1 = D9–D0 are the ADC outputs directly without being processed by video demodulator. 0 = D9–D0 are 10-bit YCbCr component video (default). With RAWADC = 1, the D9–D0 output data rate is 54Msps and the LLC clock output is 54MHz. Figure 16 shows the typical setup and hold timings of the output signals with RAWADC = 1. LLC can optionally be inverted by setting LLCINV = 1 in register 0x0D, B5. With RAWADC = 1 the ADC outputs are filtered with the digital lowpass filter before being routed to D9–D0. The ADC outputs can be directly connected to D9–D0 with- out filtering by setting RAWADC = 1 and DISAAFLT = 1 in register 0x0F, B5. REG B7 B6 B5 B4 B3 B2 B1 B0 0x0C RAWADC 0 TGEnab TGTIM TGSRC 0 CBAR Color Test Signal Register D9–D0 LLC (54MHz) ~8ns ~18.5ns ~8ns Figure 16. Typical Setup and Hold Timings in RAWADC Mode |
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