MAX9526 datasheet(14/38 Pages) MAXIM

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Low-Power, High-Performance

NTSC/PAL Video Decoder

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SEL

_54MHz

XTAL_DIS

PLLBYP

LLC_MODE

B5-4

CLOCK MODE DESCRIPTION

000

Input clock = 27MHz crystal.

Sample clock = line locked or async (autodetected).

This is the default power-up mode for the MAX9526.

000

Input clock = 27MHz crystal.

Sample clock = line locked (forced on).

000

Input clock = 27MHz crystal.

Sample clock = 2x input clock.

Invalid modes. The PLL can only be bypassed if the

input clock is 54MHz.

010

Input clock = 27MHz external clock.

Sample clock = line locked or async (autodetected).

010

Input clock = 27MHz external clock.

Sample clock = line locked (forced on).

010

Input clock = 27MHz external clock.

Sample clock = 2x input clock.

Invalid mode. 54MHz crystal not supported.

110

Input clock = 54MHz external clock.

Sample clock = line locked or async (autodetected).

110

Input clock = 54MHz external clock.

Sample clock = line locked (forced on).

110

Input clock = 54MHz external clock.

Sample clock = input clock divided by 2, then

multiplied by 2x through the PLL. This mode uses the

PLL to filter high-frequency jitter on the input source.

111

Invalid mode. The PLL can only be bypassed when

the output is not a line-locked clock.

111

Input clock = 54MHz external clock.

Sample clock = input clock. Use this mode when a

low-jitter, 54MHz input clock is used.

Table 1. MAX9526 Clock Mode Summary

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