ADuM6402 datasheet(21/24 Pages) AD

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ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404

Rev. 0 | Page 21 of 24

The preceding magnetic flux density values correspond

to specific current magnitudes at given distances from the

ADuM640x transformers. Figure 28 expresses these allowable

current magnitudes as a function of frequency for selected

distances. As shown in Figure 28, the ADuM640x are extremely

immune and can be affected only by extremely large currents

operated at high frequency very close to the component. For

the 1 MHz example, a 0.5 kA current placed 5 mm away from

the ADuM640x is required to affect component operation.

MAGNETIC FIELD FREQUENCY (Hz)

100

0.1

0.01

10k

100M

100k

10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

Figure 28. Maximum Allowable Current for

Various Current-to-ADuM640x Spacings

Note that, in combinations of strong magnetic field and high

frequency, any loops formed by PCB traces can induce error

voltages sufficiently large to trigger the thresholds of succeeding

circuitry. Exercise care in the layout of such traces to avoid this

possibility.

POWER CONSUMPTION

The VDD1 power supply input provides power to the iCoupler

data channels, as well as to the power converter. For this reason,

the quiescent currents drawn by the data converter and the

primary and secondary I/O channels cannot be determined

separately. All of these quiescent power demands have been

combined into the IDD1 (Q) current, as shown in Figure 29. The

total IDD1 supply current is equal to the sum of the quiescent

operating current; the dynamic current, IDD1 (D), demanded by

the I/O channels; and any external IISO load.

CONVERTER

PRIMARY

CONVERTER

SECONDARY

PRIMARY

DATA

INPUT/OUTPUT

4-CHANNEL

IDDP(D)

SECONDARY

DATA

INPUT/OUTPUT

4-CHANNEL

IISO(D)

IISO

IDD1(Q)

IDD1(D)

Figure 29. Power Consumption Within the ADuM640x

Dynamic I/O current is consumed only when operating a channel

at speeds higher than the refresh rate of fr. The dynamic current

of each channel is determined by its data rate. Figure 21 shows the

current for a channel in the forward direction, meaning that the

input is on the VDD1 side of the part. Figure 22 shows the current

for a channel in the reverse direction, meaning that the input is on

the VISO side of the part. Both figures assume a typical 15 pF load.

The following relationship allows the total IDD1 current to be

calculated:

IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4

(1)

where:

IDD1 is the total supply input current.

ICHn is the current drawn by a single channel determined from

Figure 21 or Figure 22, depending on channel direction.

IISO is the current drawn by the secondary side external load.

E is the power supply efficiency at 100 mA load from Figure 13

at the VISO and VDD1 condition of interest.

The maximum external load can be calculated by subtracting

the dynamic output load from the maximum allowable load.

IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4

(2)

where:

IISO (LOAD) is the current available to supply an external secondary

side load.

IISO (MAX) is the maximum external secondary side load current

available at VISO.

IISO (D)n is the dynamic load current drawn from VISO by an input

or output channel, as shown in Figure 23 and Figure 24.

The preceding analysis assumes a 15 pF capacitive load on each

data output. If the capacitive load is larger than 15 pF, the additional

current must be included in the analysis of IDD1 and IISO (LOAD).

POWER CONSIDERATIONS

The ADuM640x power input, data input channels on the

primary side, and data channels on the secondary side are all

protected from premature operation by UVLO circuitry. Below

the minimum operating voltage, the power converter holds its

oscillator inactive and all input channel drivers and refresh

circuits are idle. Outputs remain in a high impedance state to

prevent transmission of undefined states during power-up and

power-down operations.

During application of power to VDD1, the primary side circuitry

is held idle until the UVLO preset voltage is reached. At that

time, the data channels initialize to their default low output

state until they receive data pulses from the secondary side.

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