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SE97TP Datasheet(PDF) 34 Page - NXP Semiconductors

Part # SE97TP
Description  DDR memory module temp sensor with integrated SPD, 3.3 V
PDF  53 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SE97TP Datasheet(HTML) 34 Page - NXP Semiconductors

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SE97_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 August 2009
34 of 53
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
9.
Application design-in information
In a typical application, the SE97 behaves as a slave device and interfaces to a bus
master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host,
and asserts when the temperature reading exceeds the programmed values in the alarm
registers. The A0, A1 and A2 pins are directly connected to VDD or VSS without any pull-up
resistors. The SDA and SCL serial interface pins are open-drain I/Os that require pull-up
resistors, and are able to sink a maximum of 3 mA with a voltage drop less than 0.4 V.
Typical pull-up values for SCL and SDA are 10 k
Ω, but the resistor values can be changed
in order to meet the rise time requirement if the capacitance load is too large due to
routing, connectors, or multiple components sharing the same bus.
Fig 22. Typical application showing SE97 interfacing with 3.3 V host
002aab354
HOST
CONTROLLER
SE97
A0
A1
A2
SCL
SDA
EVENT
VDD
10 k
(3
×)
VSS
slave
master
3.3 V
Fig 23. SE97 interfacing with 1.1 V host controller
002aad262
HOST
CONTROLLER
SE97
A0
A1
A2
SCL
SDA
EVENT
VDD
10 k
VSS
3.3 V
0.1
µF
10 k
PCA9509
mother board
0.1
µF
VCC(B)
B2
B1
EN
VCC(A)
A2
A1
10 k
10 k
SCL
SDA
EVENT
0.1
µF
1.1 V



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