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SE97TP Datasheet(PDF) 6 Page - NXP Semiconductors

Part # SE97TP
Description  DDR memory module temp sensor with integrated SPD, 3.3 V
PDF  53 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SE97TP Datasheet(HTML) 6 Page - NXP Semiconductors

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SE97_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 August 2009
6 of 53
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.
Functional description
7.1 Serial bus interface
The SE97 communicates with a host controller by means of the 2-wire serial bus
(I2C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The
device supports SMBus, I2C-bus Standard-mode and Fast-mode. The I2C-bus standard
speed is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus fast speed from 0 Hz
to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates
the SCL signal, and the SE97 uses the SCL signal to receive or send data on the SDA
line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant
Bit (MSB) is transferred first. Since SCL and SDA are open-drain, pull-up resistors must
be installed on these pins.
7.2 Slave address
The SE97 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address
that allows a total of eight devices to coexist on the same bus. The A0, A1 and A2 pins are
pulled LOW internally. The A0 pin is also overvoltage tolerant supporting 10 V software
write protect. When it is driven higher than 7.8 V, writing a special command would put the
EEPROM in reversible write protect mode (see Section 7.10.2 “Memory protection”). Each
pin is sampled at the start of each I2C-bus/SMBus access. The temperature sensor’s fixed
address is ‘0011b’. The EEPROM’s fixed address for the normal EEPROM read/write is
‘1010b’, and for EEPROM software protection command is ‘0110b’. Refer to Figure 6.
a. Temperature sensor
b. EEPROM (normal read/write)
c. EEPROM (software
protection command)
Fig 6.
Slave address
R/W
002aab304
0
0
1
1
A2
A1
A0
fixed
hardware
selectable
slave address
MSB
LSB
X
R/W
002aab351
1
0
1
0
A2
A1
A0
fixed
hardware
selectable
slave address
MSB
LSB
X
R/W
002aab352
0
1
1
0
A2
A1
A0
fixed
hardware
selectable
slave address
MSB
LSB
X



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