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ICS845204 Datasheet(PDF) 2 Page - Integrated Device Technology

Part # ICS845204
Description  CRYSTAL-TO-MLVDS PCI EXPRESS??CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PDF  13 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS845204 Datasheet(HTML) 2 Page - Integrated Device Technology

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ICS845204
CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ADVANCE INFORMATION
IDT™ / ICS™ M-LVDS CLOCK SYNTHESIZER
2
ICS845204AK SEPTEMBER 25, 2007
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1
OE0
Input
Pullup
Output enable pin for Q0/nQ0 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
2, 11
VDD
Power
Core supply pins.
3, 4
nQ3, Q3
Output
Differential output pair. M-LVDS interface levels.
5VDDO
Power
Output supply pin.
6, 8, 18, 23,
24, 27
nc
Unused
No connect.
7
FSEL0
Input
Pullup
Output frequency select pins. See Table 3A. LVCMOS/LVTTL interface levels.
9
FSEL1
Input
Pulldown
Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
10,
19
SSC0,
SSC1
Input
Pullup
Spread spectrum control pins. See Table 3B. LVCMOS/LVTTL interface levels.
12
OE3
Input
Pullup
Output enable pin for Q3/nQ3 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
13,
14
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
15
OE2
Input
Pullup
Output enable pin for Q2/nQ2 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
16, 17, 22, 30
GND
Power
Power supply ground.
20, 21
nQ2, Q2
Output
Differential output pair. M-LVDS interface levels.
25, 26
nQ1, Q1
Output
Differential output pair. M-LVDS interface levels.
28
VDDA
Power
Analog supply pin.
29
OE1
Input
Pullup
Output enable pin for Q1/nQ1 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
31, 32
nQ0, Q0
Output
Differential output pair. M-LVDS interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
Ω
RPULLDOWN
Input Pulldown Resistor
51
k
Ω



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