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ICS845204 Datasheet(PDF) 7 Page - Integrated Device Technology |
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ICS845204 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 13 page ![]() ICS845204 CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM ADVANCE INFORMATION IDT™ / ICS™ M-LVDS CLOCK SYNTHESIZER 7 ICS845204AK SEPTEMBER 25, 2007 Parameter Measurement Information, continued Offset Voltage Setup Differential Output Voltage Setup Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS845204 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a 0.01µF bypass capacitor should be connected to each VDDA pin. Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. Outputs: M-LVDS Outputs All unused M-LVDS output pairs can be either left floating or terminated with 100 Ω across. If they are left floating, there should be no trace attached. out out M-LVDS DC Input ➤ VOS/∆ VOS V DD ➤ 100 out out M-LVDS DC Input VOD/∆ VOD V DD 100 VDD VDDA 3.3V 10 Ω 10µF .01µF .01µF |
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