ST7033

Ver 1.1

26/39

2009/07/17

(VDD1 = 2.8V , Ta =25°C )

Rating

Item

Signal

Symbol

Condition

Min.

Max.

Units

Address hold time

tAH8

15

—

Address setup time

tAW8

120

—

Address setup time

tAS8

80

—

System cycle time

A0

tCYC8

450

—

Enable L pulse width (WRITE)

tCCLW

120

—

Enable H pulse width (WRITE)

/WR

tCCHW

100

—

WRITE Data setup time

tDS8

90

—

WRITE Address hold time

D0 to D7

tDH8

60

—

ns

(VDD1 = 1.8V , Ta =25°C)

Rating

Item

Signal

Symbol

Condition

Min.

Max.

Units

Address hold time

tAH8

30

—

Address setup time

tAW8

150

—

Address setup time

tAS8

100

—

System cycle time

A0

tCYC8

550

—

Enable L pulse width (WRITE)

tCCLW

170

—

Enable H pulse width (WRITE)

/WR

tCCHW

150

—

WRITE Data setup time

tDS8

120

—

WRITE Address hold time

D0 to D7

tDH8

70

—

ns

Notes1:The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely

fast,(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.

Notes2: All timing is specified using 20% and 80% of VDD1 as the reference.

Notes3: tCCLW and tCCLR are specified as the overlap between /CSB being “L” and /WR and /RD being at the “L” level.