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ST7033 Datasheet(PDF) 18 Page - Sitronix Technology Co., Ltd. |
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ST7033 Datasheet(HTML) 18 Page - Sitronix Technology Co., Ltd. |
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18 / 39 page ![]() ST7033 Ver 1.1 18/39 2009/07/17 9-2. INSTRUCTION DESCRIPTION Display data Write 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address . The column address is increased by 1 automatically so that the microprocessor can continuously write data . During auto-increment, the column address wraps to 0 after the last column is written. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 1 Write data Write to the DDRAM Display ON/OFF This command turns the display ON and OFF. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 0 Display OFF 0 1 0 1 0 1 1 1 1 Display ON Display Normal/Reverse This command can reserve the lit and unlit without overwriting the content of the DDRAM. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 0 LCD ON Voltage 0 1 0 1 0 0 1 1 1 LCD OFF Voltage Display All Points ON/OFF The command makes it possible to force all display points ON regardless of the content of the DDRAM. Even when this is done, the DDRAM contents are maintained. This command takes priority over the Display normal/reverse command. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 0 Normal Display Mode 0 1 0 1 0 0 1 0 1 Display All Points ON When the Display all points ON command is executed when in the Display OFF mode, Power Save mode is entered. See the “Power Save mode” for detail. Page Address Set This command specifies the start page address of the DDRAM. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 0 1 0 1 1 0 0 0 0 Ser page address Column Address Set This command specifies the column address of the DDRAM. The column address is split into two sections (the upper 3-bits and lower 4-bits) when it is set. Each time the DDRAM is accessed, the column address automatically increments by +1, imaging it possible for the MCU to continuously access to the display data. After the last column address (5FH), column address returns to 00H. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 1 * X6 X5 X4 Upper bit address 0 0 0 0 0 X3 X2 X1 X0 Lower bit address Notes:’ * ‘Disabled bit |
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