ST7033

Ver 1.1

12/39

2009/07/17

DISPLAY DATA RAM (DDRAM)

The ST7033 contains a 4x96 bit static RAM that stores the display data. The display data RAM store the dot data for the

LCD.It is 4-row by 96-column addressable array. Each pixel can be selected when the column addresses are

specified.Data are written to ram directly through D0 to D3 and D4 to D7 are disabled bits. The display data from the

microprocessor correspond to the LCD common lines. The microprocessor can write to RAM through the I/O buffer. Since

the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed

without causing the LCD flicker.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line

Address repeatedly.At the beginning of each LCD frame, the contents of register are copied to the line counter which is

increased by CL signal and generates the line address for transferring the 96-bit RAM data to the display data latch circuit.

Column Address Circuit

Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM. The display

data RAM column address is specified by the Column Address Set command. The specified column address is

incremented (+1) with each display data write command. This allows the MPU display data to be accessed continuously.

ADDRESSING

Data is downloaded in bytes into the RAM matrix of ST7033 as indicated in Figure 4. The display RAM has a matrix of 4 by

96 bits. The address pointer addresses the columns. The column address ranges are: 0 to 95 (1011111), .Addresses

outside these ranges are not allowed. After the last column address (95) wraps around to 0 .