ST7033 datasheet(7/39 Pages) SITRONIX

7 / 39 page

ST7033

Ver 1.1

7/39

2009/07/17

6. PINNING DESCRIPTIONS

Pin Name

I/O

Description

Pin Count

LCD driver outputs

SEG0 to SEG95

LCD segment driver outputs.

The display data and the M signal control the output voltage of segment

driver.

Segment drover output voltage

Display data

Frame

Normal display

Reverse display

VSS

Power save mode

VSS

COM0 to COM3

LCD column driver outputs.

The internal scanning data and the M signal control the output voltage of

common driver.

Common drover output voltage

Display data

Frame

Normal display

Reverse display

XV0

Power save mode

VSS

MICROPROCESSOR INTERFACE

PS[1,0]

Microprocessor interface mode selection pins.

PS1

PS0

Interface Mode

8080-series parallel MPU interface

6800-series parallel MPU interface

4-line SPI MPU interface

3-line SPI MPU interface

/CSB

Chip select input pin.

Data/instruction I/O is enabled only when /CSB is "L". When chip select is

non-active, D7…D0 are high impedance.

/RESB

Reset input pin.

When /RESB is "L", initialization is executed.

It determines whether the data bits are data or a command.

A0=" H “: Indicates that D0 to D7 are display data.

A0=" L “: Indicates that D0 to D7 are control data.

There is no A0 pin in three line , so this pin can fix to ” H”

RW_WR

Read/Write operation control pin (if using Parallel interface).

MPU Type

RW_WR

Interface Mode

6800-series

R/W

R/W=”H”: Read;

R/W=”L”: Write.

8080-series

/WR

Signals (Instruction or Data) on

data bus will be latched at the

raising edge of this signal.

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