LPC1313 datasheet(25/53 Pages) NXP

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LPC1311_13_42_43_1

Product data sheet

Rev. 01 — 11 December 2009

25 of 53

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.18.2 Brownout detection

The LPC1311/13/42/43 includes four levels for monitoring the voltage on the VDD(3V3) pin.

If this voltage falls below one of the four selected levels, the BOD asserts an interrupt

signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable

signal by reading a dedicated status register. An additional threshold level can be selected

to cause a forced reset of the chip.

7.18.3 Code security (Code Read Protection - CRP)

This feature of the LPC1311/13/42/43 allows user to enable different levels of security in

the system so that access to the on-chip ﬂash and use of the JTAG and ISP can be

restricted. When needed, CRP is invoked by programming a speciﬁc pattern into a

dedicated ﬂash location. IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding

ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and ﬂash ﬁeld updates are needed but all sectors can not be erased.

2. CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the JTAG pins and the ISP. This mode effectively disables ISP override using PIO0_1

pin, too. It is up to the user’s application to provide (if needed) ﬂash update

mechanism using IAP calls or call reinvoke ISP command to enable ﬂash update via

UART0.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the

LPC13xx user manual.

7.18.4 Boot loader

The boot loader controls initial operation after reset and also provides the means to

program the ﬂash memory. This could be initial programming of a blank device, erasure

and re-programming of a previously programmed device, or programming of the ﬂash

memory by the application program in a running system.

The boot loader code is executed every time the part is reset or powered up. The loader

can either execute the ISP command handler or the user application code, or, on the

LPC134x, it can obtain the boot image as an attached MSC device through USB. A LOW

level during reset at the PIO0_1 pin is considered an external hardware request to start

the ISP command handler or the USB device enumeration. The state of PIO0_3

determines whether the UART or USB interface will be used (LPC134x only).

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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