LPC1313 datasheet(42/53 Pages) NXP

42 / 53 page

LPC1311_13_42_43_1

Product data sheet

Rev. 01 — 11 December 2009

42 of 53

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.5 SSP interface

[1]

Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (speciﬁed in the SSP0CR0

[2]

Tamb = −40 °C to 85 °C; VDD(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V.

[3]

Tcy(clk) = 12 × Tcy(PCLK).

[4]

Tamb = 25 °C; VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V.

Fig 22. I2C-bus pins clock timing

002aae860

tSU;DAT

SDA

SCL

Table 15.

Dynamic characteristics of SSP pins in SPI mode

Symbol

Parameter

Conditions

Min

Max

Unit

Tcy(PCLK)

PCLK cycle time

13.9

Tcy(clk)

clock cycle time

[1]

27.8

SSP master

tDS

data set-up time

in SPI mode

[2]

Tcy(clk)

tDH

data hold time

in SPI mode

[2]

-0

tv(Q)

data output valid time

in SPI mode

[2]

-10

th(Q)

data output hold time

in SPI mode

[2]

-0

SSP slave

tDS

data set-up time

in SPI mode

[3][4]

tDH

data hold time

in SPI mode

[3][4]

× Tcy(PCLK) + 4

tv(Q)

data output valid time

in SPI mode

[3][4]

-3

× Tcy(PCLK) + 11

th(Q)

data output hold time

in SPI mode

[3][4]

-2

× Tcy(PCLK) + 5

LPC1313 Datasheet(PDF) 42 Page - NXP Semiconductors

LPC1313 Datasheet(HTML) 42 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL