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LPC1313 Datasheet(PDF) 47 Page - NXP Semiconductors |
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LPC1313 Datasheet(HTML) 47 Page - NXP Semiconductors |
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47 / 53 page ![]() LPC1311_13_42_43_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 11 December 2009 47 of 53 NXP Semiconductors LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 11.4 Standard I/O pad configuration Figure 29 shows the possible pin modes for standard I/O pins. The pull-up and pull-down resistors (Rpu and Rpd) can be enabled or disabled. The default value for each standard port pin is input with Rpu enabled. For details on pin modes and hysteresis control, see the LPC13xx user manual. Fig 28. Slave mode operation of the on-chip oscillator LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 29. Standard I/O pad configuration PIN VDD(IO) VSS Rpd Rpu enable output input 002aae828 hysteresis control |
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