LPC2290 datasheet(17/41 Pages) NXP

17 / 41 page

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

17 of 41

NXP Semiconductors

LPC2290

16/32-bit ARM microcontroller with external memory interface

6.5 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

6.6 External memory controller

The external Static Memory Controller is a module which provides an interface between

the system bus and external (off-chip) memory devices. It provides support for up to four

independently conﬁgurable memory banks (16 MB each with byte lane enable control)

simultaneously. Each memory bank is capable of supporting SRAM, ROM, ﬂash EPROM,

burst ROM memory, or some external I/O devices.

Each memory bank may be 8-bit, 16-bit, or 32-bit wide.

6.7 General purpose parallel I/O and Fast I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.7.1 Features

• Direction control of individual bits.

• Separate control of output set and clear.

SPI1/SSP

Source: SPI1 SPI Interrupt Flag (SPIF), Mode Fault (MODF)

Source: SSP (available in LPC2290/01 only)

TX FIFO at least half empty (TXRIS)

RX FIFO at least half full (RXRIS)

Receive Timeout condition (RTRIS)

Receive Overrun (RORRIS)

PLL

PLL Lock (PLOCK)

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

System Control

External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

External Interrupt 2 (EINT2)

External Interrupt 3 (EINT3)

A/D

ADC

CAN

1 ORed CAN Acceptance Filter

CAN1 (TX int, RX int)

20, 21

CAN2 (TX int, RX int)

22, 23

Table 4.

Interrupt sources …continued

Block

Flag(s)

VIC channel #

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