Block Guide — S12BDM V4

13

BDMACT — BDM active status

This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled

and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the

standard BDM firmware as part of the exit sequence to return to user code and remove the BDM

memory from the map.

1 = BDM active

0 = BDM not active

ENTAG — Tagging enable

This bit indicates whether instruction tagging in enabled or disabled. It is set when the TAGGO

command is executed and cleared when BDM is entered. The serial system is disabled and the tag

function enabled 16 cycles after this bit is written. BDM cannot process serial commands while

tagging is active.

1 = Tagging enabled

0 = Tagging not enabled or BDM active

SDV — Shift data valid

This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a

firmware read command or after data has been received as part of a firmware write command. It is

cleared when the next BDM command has been received or BDM is exited. SDV is used by the

standard BDM firmware to control program flow execution.

1 = Data phase of command is complete

0 = Data phase of command not complete

TRACE — TRACE1 BDM firmware command is being executed

This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set as long

as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next

command that is not a TRACE1 command is recognized.

1 = TRACE1 command is being executed

0 = TRACE1 command is not being executed

CLKSW — Clock switch

The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware

BDM command. A 150 cycle delay at the clock speed that is active during the data portion of the

command will occur before the new clock source is guaranteed to be active. The start of the next BDM

command uses the new clock for timing subsequent BDM communications.

Table 3-2 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (Pll select

from the clock and reset generator) bits.