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HCS12 Datasheet(PDF) 18 Page - Motorola, Inc |
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HCS12 Datasheet(HTML) 18 Page - Motorola, Inc |
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18 / 34 page ![]() Block Guide — S12BDM V4 18 After being enabled, BDM is activated by one of the following(1): • Hardware BACKGROUND command • BDM external instruction tagging mechanism • CPU BGND instruction • Breakpoint sub-block’s force or tag mechanism(2) When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by the breakpoint sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE: If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses $FF00 to $FFFF. BDM registers are mapped to addresses $FF00 to $FF07. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs. 4.3 BDM Hardware Commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, EEPROM, FLASH EEPROM, I/O and control registers, and all external memory. Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free CPU bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. The BDM hardware commands are listed in Table 4-1. NOTES: 1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is only available on systems that have a a Breakpoint or a Debug sub-block. |
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