Block Guide — S12BDM V4

24

The receive cases are more complicated. Figure 4-3 shows the host receiving a logic 1 from the target

system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the

host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the

BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must

release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the

perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it

started the bit time.

Figure 4-3 BDM Target-to-Host Serial Bit Timing (Logic 1)

HIGH-IMPEDANCE

EARLIEST

START OF

NEXT BIT

R-C RISE

10 CYCLES

10 CYCLES

HOST SAMPLES

BKGD PIN

PERCEIVED

START OF BIT TIME

BKGD PIN

CLOCK

TARGET SYSTEM

HOST

DRIVE TO

BKGD PIN

TARGET SYSTEM

SPEEDUP

PULSE

HIGH-IMPEDANCE

HIGH-IMPEDANCE