Block Guide — S12BDM V4

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brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host

for transmit cases and the target for receive cases.

The timing for host-to-target is shown in Figure 4-2 and that of target-to-host in Figure 4-3 and

Figure 4-4. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since

the host and target are operating from separate clocks, it can take the target system up to one full clock

cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the

host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle

earlier. Synchronization between the host and target is established in this manner at the start of every bit

time.

Figure 4-2 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a

target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the

host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten

target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic

requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1

transmission.

Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven

signals.

Figure 4-2 BDM Host-to-Target Serial Bit Timing

EARLIEST

START OF

NEXT BIT

TARGET SENSES BIT

10 CYCLES

SYNCHRONIZATION

UNCERTAINTY

CLOCK

TARGET SYSTEM

HOST

TRANSMIT 1

HOST

TRANSMIT 0

PERCEIVED

START OF BIT TIME