DSP56303 datasheet(32/108 Pages) FREESCALE

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DSP56303 Technical Data, Rev. 11

2-12

Freescale Semiconductor

Specifications

2.5.5

External Memory Expansion Port (Port A)

2.5.5.1 SRAM Timing

Table 2-8.

SRAM Read and Write Accesses

No.

Characteristics

Symbol

Expression1

100 MHz

Unit

Min

Max

100

Address valid and AA assertion pulse width2

tRC, tWC

(WS + 1)

× T

C −4.0

≤WS ≤3]

(WS + 2)

× TC −4.0

≤WS ≤7]

(WS + 3)

× TC −4.0

[WS

≥ 8]

16.0

56.0

106.0

—

101

Address and AA valid to WR assertion

tAS

0.25

× TC −2.0

[WS = 1]

0.75

× T

C −2.0

≤WS ≤3]

1.25

× TC −2.0

[WS

≥ 4]

0.5

5.5

10.5

—

102

WR assertion pulse width

tWP

1.5

× TC −4.0

[WS = 1]

× TC −4.0

≤WS ≤3]

(WS

−0.5) × T

C −4.0

[WS

≥ 4]

11.0

16.0

31.0

—

103

WR deassertion to address not valid

tWR

0.25

× T

C −2.0

≤WS ≤3]

1.25

× TC −4.0

≤WS ≤7]

2.25

× TC −4.0

[WS

≥ 8]

0.5

8.5

18.5

—

104

Address and AA valid to input data valid

tAA, tAC

(WS + 0.75)

× TC −5.0

[WS

≥ 1]

—12.5

105

RD assertion to input data valid

tOE

(WS + 0.25)

× TC – 5.0

[WS

≥ 1]

—7.5

106

RD deassertion to data not valid (data hold time)

tOHZ

0.0

—

107

Address valid to WR deassertion2

tAW

(WS + 0.75)

× T

C −4.0

[WS

≥ 1]

13.5

—

108

Data valid to WR deassertion (data setup time)

tDS (tDW)(WS −0.25) × TC −3.0

[WS

≥ 1]

4.5

—

109

Data hold time from WR deassertion

tDH

0.25

× T

C −2.0

≤WS ≤3]

1.25

× TC −2.0

≤WS ≤7]

2.25

× TC −2.0

[WS

≥ 8]

0.5

10.5

20.5

—

110

WR assertion to data active

—

0.75

× TC −3.7

[WS = 1]

0.25

× T

C – 3.7

≤WS ≤3]

–0.25

× TC −3.7

[WS

≥ 4]

3.8

–1.2

–6.2

—

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