DSP56303 datasheet(44/108 Pages) FREESCALE

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DSP56303 Technical Data, Rev. 11

2-24

Freescale Semiconductor

Specifications

2.5.5.3 Synchronous Timings

Table 2-13.

External Bus Synchronous Timings1,2

No.

Characteristics

Expression3,4,5

100 MHz

Unit

Min

Max

198

CLKOUT high to address, and AA valid

0.25

× TC + 4.0

—

6.5

199

CLKOUT high to address, and AA invalid6

0.25

× T

2.5

—

200

TA valid to CLKOUT high (set-up time)

4.0

—

201

CLKOUT high to TA invalid (hold time)

0.0

—

202

CLKOUT high to data out active

0.25

× TC

2.5

—

203

CLKOUT high to data out valid

0.25

× T

C + 4.0

—

6.5

204

CLKOUT high to data out invalid

0.25

× TC

2.5

—

205

CLKOUT high to data out high impedance

0.25

× T

—2.5

206

Data in valid to CLKOUT high (set-up)

4.0

—

207

CLKOUT high to data in invalid (hold)

0.0

—

208

CLKOUT high to RD assertion

maximum: 0.75

× TC + 2.5

6.7

10.0

209

CLKOUT high to RD deassertion

0.0

4.0

210

CLKOUT high to WR assertion

maximum: 0.5

× TC + 4.3

for WS = 1 or WS

≥ 4

for 2

≤WS ≤3

5.0

0.0

9.3

4.3

211

CLKOUT high to WR deassertion

0.0

3.8

Notes:

Use external bus synchronous timings only for reference to the clock and

not for relative timings.

Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

WS is the number of wait states specified in the BCR.

If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

Use the expression to compute the maximum or minimum value listed, as appropriate. For timing 210, the minimum is an

absolute value.

T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set. when this mode is

enabled, use the status of BR (See T212) to determine whether the access referenced by A[0–17] is internal or external.

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