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P5DF081 Datasheet(PDF) 4 Page - NXP Semiconductors |
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P5DF081 Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 36 page ![]() P5DF081_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Objective short data sheet PUBLIC Rev. 1 — 12 August 2010 191710 4 of 36 NXP Semiconductors P5DF081 MIFARE SAM AV2 7. Pinning information 7.1 Pinning 7.2 Pin description 8. Functional specification 8.1 Hardware interface 8.1.1 Contact interface The pad assignment and the electrical characteristics are fully compliant with ISO/IEC 7816 (part 2 and part 3). The MIFARE SAM AV2 operates with Class A and Class B interface devices. An internal charge pump provides the EEPROM programming voltage. Note that pad C6 is not a programming voltage input but is an output line for the clock signal for I2C communication to the RC222 reader chip. Pad C8 is used as data line to the reader chip. These two pads for connection to the RC222 are the only ones deviating from the ISO standard pin assignment. 8.1.2 External clock frequency and bit rates The basic operation frequency of the MIFARE SAM AV2 is 3.5712 MHz. With this frequency the following standard bit rates can be reached using ISO/IEC 7816 transmission factors F and D. The MIFARE SAM AV2 supports significantly higher transmission speeds. Fig 2. Pin configuration 001aam116 C1 VCC C5 GND C2 RST_N C6 IO3 C3 CLK_N C7 IO1 C4 n.c. C8 IO2 Table 3. Pin description ISO/IEC 7816/MIFARE SAM AV2 ISO/IEC 7816 MIFARE SAM AV2 Pad Symbol Symbol Pad Description C1 VCC VCC C1 power supply voltage input C2 RST RST_N C2 reset input, active LOW C3 CLK CLK_N C3 clock input C4 reserved n.c. C4 n.c. C5 GND GND C5 ground (reference voltage) input C6 VPP IO3 C6 used for I2C communication to RC222 (SCLK) C7 IO1 IO1 C7 input/output for serial data (host communication) C8 reserved IO2 C8 used for I2C communication to RC222 (SDATA) |
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