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82X38 Datasheet(PDF) 21 Page - Intel Corporation

Part # 82X38
Description  Express Chipset
PDF  342 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82X38 Datasheet(HTML) 21 Page - Intel Corporation

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Datasheet
21
Introduction
1.2.4
PCI Express* Interface
The MCH supports two 16-lane (x16) PCI Express ports. The PCI Express ports are
compliant to the PCI Express* Base Specification revision 2.0. The x16 ports operate at
a frequency of 5 Gb/s on each lane while employing 8b/10b encoding, and support a
maximum theoretical bandwidth of 8.0 GB/s in each direction.
The PCI Express interface includes:
• Two, 16-lane PCI Express ports intended for external device attach, compatible to
the PCI Express* Base Specification, Revision 2.0.
• PCI Express frequency of 2.5 GHz resulting in 5.0 Gb/s each direction per lane.
• Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface
• Maximum theoretical realized bandwidth on the interface of 8 GB/s in each
direction simultaneously, for an aggregate of 16 GB/s when x16.
• PCI Express Enhanced Addressing Mechanism allows for accessing the device
configuration space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Supports traditional AGP style traffic (asynchronous non-snooped, PCI Express-
relaxed ordering)
• Hierarchical PCI-compliant configuration mechanism for downstream devices
(i.e., normal PCI 2.3 Configuration space as a PCI-to-PCI bridge).
• Supports “static” lane numbering reversal. This method of lane reversal is
controlled by a Hardware Reset strap, and reverses both the receivers and
transmitters for all lanes (e.g., TX[15]->TX[0], RX[15]->RX[0]). This method is
transparent to all external devices and is different than lane reversal as defined in
the PCI Express Specification. In particular, link initialization is not affected by
static lane reversal.
• When two, 16-lane PCI Express ports are used, the second port supports either PCI
Express Gen1.1 I/O cards with x8, x4 or x1 lanes or PCI Express Gen1/Gen2
Graphics cards with x16 or x1 lanes.



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