82X38 datasheet(22/342 Pages) INTEL

22 / 342 page

Introduction

Datasheet

1.2.5

MCH Clocking

•

Differential host clock of 200/266/333 MHz. Supports FSB transfer rates of

800/1066/1333 MT/s.

• Differential memory clocks of 333/400/533 MHz. Supports memory

transfer rates of DDR2-667, DDR2-800, DDR3-800, and DDR3-1067.

•

The PCI Express* PLL of 100 MHz Serial Reference Clock generates the PCI

Express core clock of 250 MHz.

• All of the above clocks are capable of tolerating Spread Spectrum clocking.

•

Host, memory, and PCI Express PLLs are disabled until PWROK is asserted.

1.2.6

Power Management

MCH Power Management support includes:

• PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)

• SMRAM space remapping to A0000h (128 KB)

• Supports extended SMRAM space above 256 MB, and cacheable (cacheability

controlled by processor)

• ACPI Rev 1.0b compatible power management

• Supports processor states: C0, C1, and C2

• Supports System states: S0, S1, S3 (Cold), and S5

• Supports processor Thermal Management 2 (TM2)

• Supports Manageability states M0, M1–S3, M1–S5, Moff–S3, Moff–S5, Moff-M1

1.2.7

Thermal Sensor

MCH Thermal Sensor support includes:

• Catastrophic Trip Point support for emergency clock gating for the MCH

• Hot Trip Point support for SMI generation

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82X38 Datasheet(PDF) 22 Page - Intel Corporation