82X38 datasheet(49/342 Pages) INTEL

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System Address Map

3.7.4

SMM Control Combinations

The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit

allows software to write to the SMM ranges without being in SMM mode. BIOS software

can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range

access to only SMM mode accesses. The D_CLS bit causes SMM (both CSEG and TSEG)

data accesses to be forwarded to the DMI Interface or PCI Express. The SMM software

can use this bit to write to video memory while running SMM code out of DRAM.

3.7.5

SMM Space Decode and Transaction Handling

Only the processor is allowed to access SMM space. PCI Express and DMI Interface

originated transactions are not allowed to SMM space.

3.7.6

Processor WB Transaction to an Enabled SMM Address

Space

Processor Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space must

be written to the associated SMM DRAM even though D_OPEN=0 and the transaction is

not performed in SMM mode. This ensures SMM space cache coherency when cacheable

extended SMM space is used.

3.7.7

SMM Access Through TLB

Accesses through TLB address translation to enabled SMM DRAM space are not allowed.

Writes will be routed to Memory address 000C_0000h with byte enables de-asserted

and reads will be routed to Memory address 000C_0000h. If a TLB translated address

hits enabled SMM DRAM space, an error is recorded.

PCI Express and DMI Interface originated accesses are never allowed to access SMM

space directly or through the TLB address translation. If a TLB translated address hits

enabled SMM DRAM space, an error is recorded.

PCI Express and DMI Interface write accesses through GMADR range will be snooped.

Assesses to GMADR linear range (defined via fence registers) are supported. PCI

Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when

translated, the resulting physical address is to enabled SMM DRAM space, the request

will be remapped to address 000C_0000h with de-asserted byte enables.

Table 7.

SMM Control Table

G_SMRAME

D_LCK

D_CLS

D_OPEN

Processor

in SMM

Mode

SMM Code

Access

SMM Data

Access

Disable

Enable

Disable

Invalid

Disable

Enable

Disable

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