L2500 datasheet(13/91 Pages) INTEL

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Datasheet

Low Power Features

2.1.1

Core Low-Power States

2.1.1.1

C0 State

This is the normal operating state for the Intel Core Duo processor and Intel Core Solo

processor.

2.1.1.2

C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when the processor core executes the HALT

instruction. The processor core will transition to the C0 state upon the occurrence of

SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the

processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® Architecture Software

Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information.

The system can generate an STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

While in AutoHALT Powerdown state, the dual core processor will process bus snoops

and snoops from the other core, and the single core processor will process only the bus

snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to

process the snoop and then return to the AutoHALT Powerdown state.

2.1.1.3

C1/MWAIT Powerdown State

MWAIT is a low power state entered when the processor core executes the MWAIT

instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state

except that there is an additional event that can cause the processor core to return to

the C0 state: the Monitor event. See the Intel® Architecture Software Developer's

Manual, Volumes 2A/2B: Instruction Set Reference, for more information.

2.1.1.4

Core C2 State

Individual cores of the Intel Core Duo processor and Intel Core Solo processor can

enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2)

instruction, but the processor will not issue a Stop Grant Acknowledge special bus cycle

unless the STPCLK# pin is also asserted.

While in C2 state, the dual core processor will process bus snoops and snoops from the

other core, and the single core processor will process only the bus snoops. The

processor core will enter a snoopable sub-state (not shown in Figure 2) to process the

snoop and then return to the C2 state.

L2500 Datasheet(PDF) 13 Page - Intel Corporation