L2500 datasheet(57/91 Pages) INTEL

57 / 91 page

Datasheet

Package Mechanical Specifications and Pin Information

THERMTRIP#

Output

The processor protects itself from catastrophic overheating by use

of an internal thermal sensor. This sensor is set well above the

normal operating temperature to ensure that there are no false

trips. The processor will stop all execution when the junction

temperature exceeds approximately 125°C. This is signalled to the

system by the THERMTRIP# (Thermal Trip) pin.

For termination requirements please contact your Intel

representative.

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used

by debug tools.

Please contact your Intel representative for termination

requirements and implementation details.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY#

must connect the appropriate pins of both FSB agents.

Please contact your Intel representative for termination

requirements and implementation details.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

Please contact your Intel representative for termination

requirements and implementation details.

Input

Processor core power supply.

CCA

Input

CCA provides isolated power for the internal processor core PLL’s.

Please contact your Intel representative for complete

implementation details.

CCP

Input

Processor I/O Power Supply.

CCSENSE

Output

CCSENSE together with VSSSENSE are voltage feedback signals to

IMVP6 that control the 2.1-mΩ loadline at the processor die. It

should be used to sense voltage near the silicon with little noise.

Please contact your Intel Representative for more information

regarding termination and routing recommendations.

VID[6:0]

Output

VID[6:0] (Voltage ID) pins are used to support automatic selection

of power supply voltages (VCC). Unlike some previous generations

of processors, these are CMOS signals that are driven by the Intel

Core Duo processor and Intel Core Solo processor. The voltage

supply for these pins must be valid before the VR can supply VCC to

the processor. Conversely, the VR output must be disabled until the

voltage supply for the VID pins becomes valid. The VID pins are

needed to support the processor voltage specification variations.

See Table 2 for definitions of these pins. The VR must supply the

voltage that is requested by the pins, or disable itself.

SSSENSE

Output

SSSENSE together with VCCSENSE are voltage feedback signals to

Intel® MVP6 that control the 2.1-mΩ loadline at the processor die.

It should be used to sense ground near the silicon with little noise.

Please contact your Intel Representative for more information

regarding termination and routing recommendations.

Table 17.

Signal Description (Sheet 9 of 9)

Name

Type

Description

L2500 Datasheet(PDF) 57 Page - Intel Corporation

L2500 Datasheet(HTML) 57 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL