CC430F613 datasheet(53/120 Pages) TI1

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ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F613x

CC430F612x

CC430F513x

www.ti.com

SLAS554E – MAY 2009 – REVISED NOVEMBER 2010

PMM, Brown-Out Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BORH on voltage,

V(DVCC_BOR_IT–)

| dDVCC/dt | < 3 V/s

1.45

DVCC falling level

BORH off voltage,

V(DVCC_BOR_IT+)

| dDVCC/dt | < 3 V/s

0.80

1.30

1.50

DVCC rising level

V(DVCC_BOR_hys)

BORH hysteresis

250

Pulse length required at

tRESET

RST/NMI pin to accept a

µs

reset

PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Core voltage, active

VCORE3(AM)

2.4 V

≤ DVCC ≤ 3.6 V

1.90

mode, PMMCOREV = 3

Core voltage, active

VCORE2(AM)

2.2 V

≤ DVCC ≤ 3.6 V

1.80

mode, PMMCOREV = 2

Core voltage, active

VCORE1(AM)

2.0 V

≤ DVCC ≤ 3.6 V

1.60

mode, PMMCOREV = 1

Core voltage, active

VCORE0(AM)

1.8 V

≤ DVCC ≤ 3.6 V

1.40

mode, PMMCOREV = 0

Core voltage, low-current

VCORE3(LPM)

2.4 V

≤ DVCC ≤ 3.6 V

1.94

mode, PMMCOREV = 3

Core voltage, low-current

VCORE2(LPM)

2.2 V

≤ DVCC ≤ 3.6 V

1.84

mode, PMMCOREV = 2

Core voltage, low-current

VCORE1(LPM)

2.0 V

≤ DVCC ≤ 3.6 V

1.64

mode, PMMCOREV = 1

Core voltage, low-current

VCORE0(LPM)

1.8 V

≤ DVCC ≤ 3.6 V

1.44

mode, PMMCOREV = 0

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