TDA9898HLSLASHV3 datasheet(52/103 Pages) NXP

52 / 103 page

TDA9897_TDA9898_4

Product data sheet

Rev. 04 — 25 May 2009

52 of 103

NXP Semiconductors

TDA9897; TDA9898

Multistandard hybrid IF processing

PSRR

power supply ripple

rejection

residual spurious at

nominal differential output

voltage dependent on

power supply ripple at

70 Hz; see Figure 11

-50

Single reference QSS intercarrier mixer; pins OUT1A and OUT1B

VOUT1A

voltage on pin OUT1A (DC)

1.8

2.0

2.2

VOUT1B

voltage on pin OUT1B (DC)

1.8

2.0

2.2

Ibias(int)

internal bias current (DC)

for emitter-follower

2.0

2.5

Isink(o)(max)

maximum output sink

current

DC and AC

1.4

1.7

Isource(o)(max)

maximum output source

current

DC and AC; with external

resistor to GND

3.0

output resistance

output active;

single-ended to GND

Ω

output inactive; internal

resistance to GND

800

Ω

Vo(RMS)

RMS output voltage

IF intercarrier

single-ended to GND;

B/G standard;

SC1 on; SC2 off;

see Figure 9 and Table 21

internal BP via FM AGC

140

180

internal BP

170

230

IF intercarrier

single-ended to GND;

L standard;

without modulation;

see Figure 9 and Table 21

W7[5] = 0;

internal BP + 6 dB

140

180

W7[5] = 1;

internal BP + 6 dB

W7[5] = 0; internal BP

W7[5] = 1; internal BP

f−3dB(ic)u

upper intercarrier cut-off

frequency

internal sound band-pass

off

MHz

αimage

image rejection

band-pass off;

−8 MHz to 0 MHz

Vinterf(RMS)

RMS interference voltage

fundamental wave and

harmonics

-2

Table 53.

Characteristics …continued

VP =5V; Tamb =25 °C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (fPC = 38.375 MHz;

fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TDA9898HL/V3 Datasheet(PDF) 52 Page - NXP Semiconductors

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