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FX629 Datasheet(PDF) 3 Page - CML Microcircuits |
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FX629 Datasheet(HTML) 3 Page - CML Microcircuits |
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3 / 10 page ![]() 3 Pin Number Function No connection Decoder Output : The recovered analogue signal is output at this pin, it is the buffered output of a bandpass filter and requires external components. During "Powersave" this output is o/c. No connection Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent non- operational state. When at a logical '1' the codec operates normally. Internal 1M Ω Pullup. Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the decoder so that the decoder output goes to V DD/2. When this pin is at a logical '1' the decoder operates as normal. Internal 1M Ω Pullup. Decoder Input : The received digital signal input. Internal 1M Ω Pullup. Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins. Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A logical '0' sets a 4-bit companding algorithm. Internal 1M Ω Pullup. Clock Mode 2 : Clock Mode 1 Clock Mode 2 Facility Clock Mode 1 : 0 0 External clocks Internal 1M Ω 0 1 Internal, 64kb/s = f ÷ 16 Pullups. 1 0 Internal, 32kb/s = f ÷ 32 1 1 Internal, 16kb/s = f ÷ 64 Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data clock frequencies are available at the ports for external circuit synchronization. Independent or common data rate inputs to Encode and Decode data clock ports may be employed in the External Clocks mode. Optimum performance will be achieved when the applied external clocks are synchronous with the master Xtal/clock, and a sub-multiple of 128kHz. V DD : Positive Supply. A single + 5 volt power supply is required. FX629J 12 13 14 15 16 17 18 19 20 21 22 |
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