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FX629 Datasheet(PDF) 1 Page - CML Microcircuits

Part # FX629
Description  Delta Modulation Codec
PDF  10 Pages
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Manufacturer  CMLMICRO [CML Microcircuits]
Direct Link  http://www.cmlmicro.com
Logo CMLMICRO - CML Microcircuits

FX629 Datasheet(HTML) 1 Page - CML Microcircuits

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The encoder has an enable function for use in
multiplexer applications.
Encoder and Decoder forced idle facilities are
provided, forcing a 10101010..... pattern in
encode and a V
DD/2 bias in decode.
The companding circuits may be operated with
a pin-selected 3 or 4-bit algorithm.
The powersave facility puts the device into the
standby mode thereby reducing current
consumption when not operating.
A reference 1.024MHz oscillator uses an
external clock pulse or Xtal input.
The FX629 is a low-power, 5 volt CMOS
device and is available in 22-pin cerdip DIL
package.
CML Semiconductor Products
PRODUCT INFORMATION
Powersave Facility
Single 5V CMOS Process
Full-Duplex CVSD* Codec
Features/Applications
Designed to Meet Mil-Std-188-113
Military Communications
Delta MUX, Switch and Phone
Applications
Single-Chip Full-Duplex Codec
On-Chip Input and Output Filters
Programmable Sampling Clocks
3 or 4-bit Compand Algorithm
Forced Idle Facility
The FX629 is an LSI circuit designed as a
*Continuously Variable Slope Delta Codec and
is intended for use in military communications
systems.
Designed to meet Mil-Std-188-113 with
external components, the device is suitable for
applications in military Delta Multiplexers,
switches and phones.
Encoder input and decoder output filters are
incorporated on-chip. Sampling clock rates can
be programmed to 16, 32 or 64 k bits/second
from an internal clock generator or may be
externally applied in the range 8 to 64 k bits/
second. Sampling clock frequencies are output
for the synchronization of external circuits.
Brief Description
Fig.1 Internal Block Diagram
DECODER DATA CLOCK
MODE 2
MODE 1
ENCODER DATA CLOCK
XTAL
DATA ENABLE
ENCODER FORCE IDLE
DECODER INPUT
MOD
ENCODER INPUT
DEMOD
XTAL/CLOCK
ENCODER OUTPUT
DECODER OUTPUT
CLOCK RATE
GENERATORS
SAMPLING RATE
CONTROL
ALGORITHM
POWERSAVE
3 or 4-BIT
CLOCK MODE
LOGIC
DECODER FORCE IDLE
f 3
f 1
V SS
VDD
VBIAS
f 0
f 1
f 2
FX629
Publication D/629/2 July 1994
Provisional Issue
FX629 Delta Modulation Codec


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