2

Pin Number Function

Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally

derived clock is injected here. See Clock Mode pins and Figure 3.

Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML

application note D/XT/1 April 1986.

No connection

Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock

output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see

Clock Mode pins).

Encoder Output : The encoder digital output, this is a three state output whose condition is

set by Data Enable and Powersave inputs as shown :

Data Enable

Powersave

Encoder Output

1

1

Enabled

0

1

High Z (o/c)

1

0

Vss

Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and

the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the

encoder encodes as normal. Internal 1M

Ω Pullup.

Data Enable : Data is made available at the encoder output pin by control of this input. See

Encoder Output pin. Internal 1M

Ω Pullup.

No connection

Bias : Normally at V

C

Internally pulled to V

Encoder Input : The analogue signal input. Internally biased at V

are required on this input. The source impedance should be less than 100

Ω, output idle

channel noise levels will improve with an even lower source impedance. See Fig. 3.

V

FX629J

1

2

3

4

5

6

7

8

9

10

11